Field-effect transistors (FETs) are very useful devices for a variety of electronic applications, such as analog switches, amplifiers of ultra-high input impedance, and voltage-controlled resistors. They are especially useful for large-scale integration (LSI) and very large-scale integration (VLSI) digital circuits, such as those used in memory chips and microprocessors.
The FETs used in high performance complementary metal oxide semiconductor (CMOS) circuits require advanced isolation techniques for filling recessed field oxide regions. One very common isolation technique is known as LOCOS (Local Oxidation of Silicon), and is described, for example, in U.S. Pat. No. 4,965,221. While LOCOS is suitable for certain CMOS applications, it has some disadvantages. For example, the LOCOS process is often not suitable for deep submicron dimensions for density-driven memory applications, because it can result in an undesirable isolation encroachment into the active device area, commonly referred to in the industry as "bird's beak". Field doping encroachment problems can also occur.
In terms of contemporary technology, shallow trench isolation (STI) exhibits significant improvements over some aspects of the LOCOS process, especially in high density CMOS circuits. As an example, STI permits the full realization of a minimum photolithographic dimension for the isolation width of a device. Higher density circuit layouts are thus possible. Also, the use of STI can lead to greater "latch-up" immunity. STI is generally described by B. Davari et al in the 1988 IEDM 88 Technical Digest, Cat. No. 88 CH2528-8, pp. 92-95.
While the use of STI leads to many desirable circuit device properties, the technique also possesses some disadvantages. One significant drawback common in STI is the presence of "edge conduction", i.e., excessive leakage current in the upper region between the top of a filled oxide trench and an adjacent silicon mesa (FIG. 1, described below, depicts this region). FET devices which exhibit high edge conduction are characterized by significant parasitic leakage, which is very undesirable, especially in low power applications which cannot tolerate current leakage of more than about 0.1 nA/micron.
One apparent way to reduce edge conduction is to uniformly dope the entire device, i.e., both the edge and planar regions. However, this solution is not altogether satisfactory because the planar threshold, as well as the edge threshold, is increased. The amount of planar current-drive lost outweighs the gain in suppressed leakage. Furthermore, devices doped at this level are susceptible to leakage-induced threshold shifts caused by the doping-induced field gradient.
Another attempt at reducing edge conduction involves the use of an active edge mask. As an example of this technique, a layer of borosilicate glass is first deposited on the surfaces of the trenches bounding the device, and then patterned so that it remains in the areas where current leakage must be suppressed. Doping is then carried out, and the dopant diffuses around the entire trench.
While the use of an active edge mask does in fact reduce edge conduction and the accompanying parasitic leakage, additional problems also result. For example, capacitance from the source-drain diffusion regions of the device may be undesirably increased because the vertical sidewalls of the trench have been doped. Furthermore, as the device width is narrowed, the dopant on the sidewalls will raise the "substrate sensitivity", i.e., the change in threshold voltage (V.sub.t) per unit change in source-to-substrate voltage. An increase in substrate sensitivity often detracts from the performance characteristics of the device. Moreover, removal of the glass layer from the bottom corners of the etch trench can be a very difficult (but necessary) task.
Another technique for reducing edge conduction involves the use of angled ion implantation into the isolation trench sidewalls, as described, for example, by G. Fuse et al in A New Isolation Method with Boron-Implanted Sidewalls for Controlling Narrow-Width Effect, IEEE Transactions on Electron Devices, Vol. ED-34, No. 2, February, 1987, pp. 356-360. However, use of such a technique can result in many of the drawbacks evident when using the other techniques described above, e.g., an increase in substrate sensitivity and capacitance.
It should thus be apparent that a need still exists for a method of controlling excessive edge conduction in trench-isolated FETs, especially STI FETs. The method should reduce parasitic current leakage, but not adversely affect the electrical output characteristics of the device. Furthermore, the substrate sensitivity of the device should not be significantly increased when edge conduction is suppressed. Finally, the method should not involve additional process steps that complicate device fabrication, or make it more costly.